1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a structure for reducing power consumption of a semiconductor memory device. More particularly, the present invention relates to a structure for reducing power consumption of an embedded DRAM (Dynamic Random Access Memory) employed in a system LSI.
2. Description of the Background Art
In a system LSI having a DRAM integrated together with the logic of a processor or an ASIC (Application Specific IC) on a common chip, the DRAM is connected with the logic through a multibit internal data bus of 128 bits to 512 bits, for example. This internal data bus is formed of an on-chip line having parasitic capacitance and parasitic resistance smaller than those of on-board lines, and can implement higher speed data transfer than that of a general-purpose high speed DRAM. In contrast to the structure where a general-purpose DRAM is provided outside the logic and connection therebetween is provided via on-board lines, the number of external data input/output pin terminals of the logic can be reduced in the system LSI. Also, the load capacitance of the data bus lines between the logic and the DRAM can be reduced at least one order. Therefore, the system LSI can significantly reduce current consumption. By virtue of these advantages, the system LSI contributes greatly to the high performance of information equipment handling a large amount of data as in three dimensional graphic processing, image and audio processing, or the like.
FIG. 67 schematically shows an entire structure of a conventional embedded DRAM employed in a system LSI. Referring to FIG. 67, the conventional embedded DRAM includes a plurality of memory arrays MA0-MAn, sense amplifier bands SB1-SBn arranged between memory arrays MA0-MAn, and sense amplifier bands SB0 and SBn+1 arranged outside memory arrays MA0 and MAn. Each of memory arrays MA0-MAn is divided into a plurality of memory subarrays MSA by subword driver bands SWDB.
In memory subarray MSA, memory cells are arranged in rows and columns. A subword line SWL is disposed corresponding to each row. In each of memory arrays MA0-MAn, a main word line MWL is disposed commonly to the plurality of memory subarrays MSA divided by subword driver bands SWDB. Main word line MWL is arranged corresponding to a predetermined number of subword lines in each memory subarray MSA in a corresponding memory array.
In subword driver band SWDB, a subword driver is arranged corresponding to subword line SWL. This subword driver drives a corresponding subword line to a selected state according to a signal on a corresponding main word line MWL and a subdecode signal not shown.
In each of sense amplifier bands SB0-SBn+1, a sense amplifier circuit is arranged corresponding to a column of a corresponding memory array. Each of sense amplifier bands SB1-SBn is shared between adjacent memory arrays. Corresponding to each of memory arrays MA0-Man, there are arranged a row decoder for selecting a main word line according to a row address signal and a column decoder arranged in alignment with the row decoder to transmit on a column select line CSL a column select signal for selecting a column from a corresponding memory array according to a column address signal. Column select line CSL is arranged at the sense amplifier band and connects a predetermined number of sense amplifier circuits to a group of global data line pairs GIOP when selected. A predetermined number of global data line pairs GIOP are disposed extending over memory arrays MA0-MAn and each coupled with a selected sense amplifier circuit via a local data line pair LIO. By arranging a row decoder and a column decoder in alignment in row/column decoder band RCDB, the distance of transferring a column select signal through column select line CSL can be reduced to realize a high speed column selection. 128 bits to 512 bits global data line pair GIOP are provided, and coupled to a data path band DPB including a preamplifier and a write driver. In this data path band DPB, a preamplifier and write driver are arranged corresponding to each global data line pair GIOP. Global data line pair GIOP may be a data line pair that transmits both read and write data, or may be formed into a read data bus line pair transmitting read data and a separate write data line pair transmitting write data.
The embedded DRAM further includes a row address input circuit/refresh counter RAFK and a column address input circuit CAK receiving an external address of, for example, 13 bits, A0-A12, applied from the logic, a command decoder/control circuit CDC receiving an external control signal applied from the logic to generate an internal control signal specifying a designated operation, and a data input/output controller DIOK for transferring data between data path band DPB and the logic.
Command decoder/control circuit CDC receives a clock signal CLK, a clock enable signal CKE, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE and a data mask signal DM to determine an operation mode specified according to the logic states of these control signals CKE, /RAS, /CAS, /WE and DM at the rising edge of clock signal CLK. Here, xe2x80x9ccommandxe2x80x9d is represented by a combination of the logic states of these control signals CKE, /RAS, /CAS, /WE and DM at the rising edge of clock signal CLK. Data mask signal DM designates a write mask on a byte-by-byte basis for data applied to data input/output controller DIOK.
Command decoder/control circuit CDC decodes a command applied from the logic to generate an operation mode designation signal designating an operation mode instructed by this command to generate various internal control signals required for carrying out the designated operation mode. As a command, there are prepared a row active command to set a row to a selected state, a read command to designate data readout, a write command to designate data writing, a precharge command to place a selected row in a non-selected state, an auto refresh command to carry out a refresh operation, and a self refresh command to carry out self refresh, and the like.
In response to application of a row active command, row address input circuit/refresh counter RAFK accepts external address bits A0-A12 as the row address to generate an internal row address signal under control of command decoder/control circuit CDC. Row address input circuit/refresh counter RAFK includes an address buffer for buffering the applied address bits, and an address latch for latching the signals output from the buffer circuit. Refresh counter is also included in row address input circuit/refresh counter RAFK, to generate a refresh address specifying a refresh row when an auto refresh command or a self refresh command is applied. When the refresh operation is completed, the count value of the refresh counter is incremented or decremented.
Column address input circuit CAK accepts, in response to a read command or a write command, predetermined external address bits, for example, lower external address bits A0-A4 to generate an internal column address signal under control of command decoder/control circuit CDC. Column address input circuit CAK includes an address buffer and an address latch.
The internal row address signal from row address input circuit/refresh counter RAFK is applied to row predecoder RPD. The internal column address signal from column address input circuit CAK is applied to column predecoder CPD. Row predecoder RPD predecodes an applied row address signal to apply a predecoded signal to the row decoder in row/column decoder band RCDB. Column predecoder CPD predecodes an internal column address signal from column address input circuit CAK to apply a predecoded signal to the column decoder in row/column decoder band RCDB.
Upon receiving a read command or a write command, command decoder/control circuit CDC generates an internal control signal to control the operation of the preamplifier or write driver in data input/output controller DIOK and data path band DPB. Clock signal CLK is used as a reference signal for determining an internal operation timing of the embedded DRAM.
Data input/output controller DIOK inputs/outputs data in synchronization with clock signal CLK. The row address input circuit of row address input circuit/refresh counter RAFK and column address input circuit CAK accept and latch the applied address bits in synchronization with clock signal CLK.
The embedded DRAM further includes an internal voltage generation circuit for generating internal voltages VPP, VCCS, VCCP, VBL and VCP, and a block PHK including a self refresh timer to render a refresh request signal FAY active at predetermined intervals when the self refresh mode is specified (when self refresh command is applied). Internal voltage VPP is transmitted on a selected subword line SWL, and generally at a level higher than an operating power supply voltage. Voltage VCCS is the operating power supply voltage of the sense amplifier circuits in sense amplifier bands SB0-SBn+1, and is generated by an internal down converter not shown. Voltage VCCP is a periphery power supply voltage, and is applied to peripheral circuits such as the row decoder and column decoder in row/column decoder band RCDB and the preamplifier and write driver in data path band DPB.
Voltage VBL is a bit line precharge voltage that will be described afterwards. Voltage VCP is a cell plate voltage applied to a cell plate of a memory cell, and is at a level intermediate the H level voltage and the L level voltage of memory cell data. Voltages VBL and VCP are generally intermediate voltages that are xc2xd the array power supply voltage (sense power supply voltage) VCCS.
The self refresh timer of block PHK is rendered active when the self refresh mode is entered, to issue the refresh request signal FAY at predetermined intervals so that all the rows of memory arrays MA0-MAn are refreshed once in the maximum refresh time tREFmax. Refresh request signal FAY is issued at the cycle of tREFmax/Nref, where Nref is the number of times of refresh operation required to refresh all the rows in memory arrays MA0-MAn. For example, in the 4K refresh mode of Nref=4096, refresh request signal FAY is issued every 16 xcexcs when the maximum refresh time tREFmax is 64 ms.
In the self refresh mode, memory cell data in the memory arrays are refreshed at a predetermined cycle in order to retain the data stored in the memory cells. The self refresh mode is set generally when the system LSI is in a sleep mode, i.e. in a standby state over a long period of time. In this sleep mode, only the retention of the stored data in the memory cells are required. For the standpoint of power consumption, it is desirable that the refresh interval is as long as possible.
FIG. 68 shows a structure of a sense amplifier circuit in sense amplifier band and a peripheral portion thereof. Referring to FIG. 68, a sense amplifier SAK is coupled to bit lines BLL and ZBLL via a bit line isolation gate BIGL, and to bit lines BLR and ZBLR of the other memory block via a bit line isolation gate BIGR. Bit line isolation gates BIGL and BIGR are rendered conductive/non-conductive in response to bit line isolation instruction signals BLIL and BLRR, respectively.
Sense amplifier SAK differentially amplifies the potentials of a common bit line CBL coupled to bit lines BLL and BLR via respective bit line isolation gates BIGL and BIGR and a common bit line ZCBL coupled to bit lines ZBLL and ZBLR via respective bit line isolation gates BIGL and BIGR. Sense amplifier SAK includes cross-coupled P channel MOS transistors (insulated gate type field effect transistor) P1 and P2, and cross-coupled N channel MOS transistors N1 and N2.
A P channel MOS transistor P3 for sense activation and an N channel MOS transistor N3 for sense activation are provided as the sense amplifier drive circuit. P channel MOS transistor P3 is rendered conductive, in response to activation of sense amplifier activation signal ZSOP, to transmit a sense power supply voltage VCCS to a sense power node S2P of sense amplifier SAK. N channel MOS transistor N3 is rendered conductive, when sense activation signal SON is active, to couple a sense ground node S2N to the ground node. Common bit lines CBL and ZCBL are coupled to a local data line pair LIO via a column select gate CSG. Local data line pair LIO is coupled to global data lines GIO and ZGIO of a global data line pair.
Bit line precharge/equalize circuit BEQL is provided for bit lines BLL and ZBLL. Bit line precharge/equalize circuit BEQL is rendered active, in response to activation of a bit line equalize designation signal BLEQL, to transmit a bit line precharge voltage VBL to bit lines BLL and ZBLL. A bit line precharge/equalize circuit BEQR is provided for bit lines BLR and ZBLR,. Bit line precharge/equalize circuit BEQR is rendered active, in response to bit line equalize designation signal BLEQR, to transmit bit line precharge voltage VBL to bit lines BLR and ZBLR.
Subword lines SWL are provided in the direction crossing bit lines BLL and ZBLL and bit lines BLR and ZBLR, and at the crossing therebetween, a memory cell MC is arranged. In FIG. 68, a subword line SWL crossing bit lines BLL and ZBLL and a memory cell MC disposed corresponding to the crossing of subword line SWL and bit line ZBLL are shown as representative. Memory cell MC includes a memory capacitor MC to store information, and an access transistor MT formed of an N channel MOS transistor, and rendered conductive in response to the potential on subword line SWL to couple memory capacitor MQ to bit line ZBLL. The potential of a storage node SN of memory capacitor MC is determined according to the stored information. A cell plate voltage VCP is applied to a cell plate facing the storage node SN.
In a standby state, bit line isolation instruction signals BLIL and BLIR are at an H level of a boosted voltage VPP, for example, and bit line isolation gates BIGL and BIGR are conductive. Bit lines BLL, CBL and BLR are coupled together, and complementary bit lines ZBLL, ZCBL and ZBLR are coupled together. Here, bit line equalize designation signals BLEQL and BLEQR are also active. By bit line precharge/equalize circuit BEQL and BEQR, bit lines BLL, CBL and BLR as well as complementary bit lines ZBLL, ZCBL and ZBLR are precharged and equalized to the level of precharge voltage VBL.
When a row active command is applied and row access is to be made, the bit line isolation gate of the memory block including the selected row (subword line) maintains a conductive state whereas the bit line isolation gate of the non-selected memory array sharing the sense amplifier with the selected memory array (memory array including the selected subword line) attains a non-conductive state. Now, the case is considered where subword line SWL shown in FIG. 68 is selected. In this case, bit line equalize signal BLEQL attains an inactive state of an L level, and bit line precharge/equalize circuit BEQL is rendered inactive. Also, bit line isolation instruction signal BLIR is driven to an L level, and bit line isolation gate BIGR is rendered non-conductive, whereby bit lines BLR and ZBLR are disconnected from common bit lines CBL and ZCBL. In this state, bit lines BLL and ZBLL of the selected memory array attain a floating state at the level of precharge voltage VBL. Bit line equalize designation signal BLEQR is at an active state of an H level. Bit lines BLR and ZBLR are held at the level of bit line precharge voltage VBL by bit line precharge/equalize circuit BEQR.
Then, a row select operation is carried out, and the potential of the selected subword line rises. More specifically, in response to the rise of the level of subword line SWL, memory access transistor MT of memory cell MC conducts, whereby storage node SN of memory capacitor MC is coupled to a corresponding bit line (ZBLL). The charge stored in capacitor MC of this memory cell is read out onto bit line ZBLL. Since no selected memory cell is connected to bit line BLL, bit line BLL is held at the intermediate voltage level of bit line precharge voltage VBL. The potential difference xcex94V between bit lines BLL and ZBLL is represented by the following equation:
xcex94V=0.5xc2x7V(SN)xc2x7CS/(CS+CB),
where CB is the parasitic capacitance of each of bit lines BLL and ZBLL, CS is the capacitance of memory capacitor MC, and V(SN) is the potential of storage node SN.
Then, sense amplifier activation signals ZSP and SON are rendered active, whereby MOS transistors P3 and N3 for sense amplifier activation are rendered conductive. Sense power supply voltage VCCS and ground voltage are responsively transmitted to sense power supply nodes S2P and S2N, respectively, and sense amplifier SAK is rendered active to start a sense operation. Since the threshold voltages of N channel MOS transistors N1 and N2 are generally smaller than the absolute value of the threshold voltages of P channel MOS transistors P1 and P2, first the sense amplifier circuit SAK initiates the sense operation by MOS transistors N1 and N2, to amplify the potential difference transmitted from bit lines BLL and ZBLL to common bit lines CBL and ZCBL. More specifically, MOS transistors N1 and N2 drive the common bit line CBL or ZCBL of the lower potential to the level of the ground voltage. Then, P channel MOS transistors P1 and P2 drive the common bit line CBL or ZCBL of the higher potential to the level of sense power supply voltage VCCS.
When data of an L level is transmitted to common bit lines CBL and ZCBL, the voltage of the common bit line receiving the data of the L level is lower than precharge voltage VBL. In the case data of an H level is read out, the voltage of the common bit line receiving this H level data is higher than precharge voltage VBL. This means that the gate-source voltage of MOS transistors N1 and N2 is lower when data of an L level is read out than in the case where data of an H level is read out. Therefore, the sense operation of N channel MOS transistors N1 and N2 becomes slower in reading out of an L level data than in the case where an H level data is read out.
The voltage sensed by sense amplifier SAK has a level proportional to voltage V (SN) of storage node SN of memory cell MC. In order to increase the sensing margin to operate sense amplifier SAK properly, the amount of charge read out from the memory cell must be as large as possible. the voltage of storage node SN is at an L level is at the level of ground voltage VSS when L level data is stored and the voltage V (SN) of storage node SN is at the level of sense power supply voltage VCCS when data of an H level is stored in this storage node SN. In order to set, as high as possible, the voltage level of the storage node SN when data of an H level is stored in storage node SN, boosted voltage VPP is transmitted to subword line SWL. This boosted voltage VPP is sufficiently higher than the sum of sense power supply voltage VCCS and the threshold voltage of access transistor MT. By transmitting boosted voltage VPP to subword line SWL, sense power supply voltage VCCS can be transmitted to storage node SN without voltage lose due to the threshold voltage of memory access transistor MT.
Upon completion of the sense operation by sense amplifier SAK, bit lines BLL and ZBLL are driven to the level of sense power supply voltage VCCS and ground voltage, respectively. When a subsequent read command or write command (column access command) is applied, a column select operation is carried out, followed by activation of the column select signal on column select line CSL. Column select gate CSG is responsively rendered conductive, and common bit lines CBL and ZCBL are coupled to global data lines GIO and ZGIO via local data line pair LIO. Then, data writing or reading is carried out.
FIG. 69 schematically shows the cross sectional structure of a memory cell. Referring to FIG. 69, N channel impurity regions 901a and 901b are formed spaced apart from each other at the surface of a P type substrate region 900. Above the channel region between these impurity regions 901a and 901b, there is formed a first conductive layer 902 that becomes a word line WL with a not shown gate insulation film laid thereunder. Impurity region 901 is connected to a second conductive layer 903 that becomes bit line BL. Impurity region 901b is connected to a third conductive layer 904 that becomes storage node SN. Third conductive layer 904 includes a leg portion connected to impurity region 901b and a cylindrical portion of a hollow structure on the leg portion. A fourth level conductive layer 906 that becomes the cell plate electrode is arranged over this cylindrical portion with a capacitor insulation film 905 laid thereunder. Fourth level conductive layer 906 that becomes the cell plate is disposed extending over a corresponding memory subarray in units of memory subarrays, and commonly receives cell plate voltage VCP. The region of fourth level conductive layer 906 facing to cylindrical region at the upper portion of third conductive layer 904 via capacitor insulation film 905 functions as a memory cell capacitor.
Memory access transistor MT is formed of impurity regions 901a and 901b and first level conductive layer 902. Substrate region 900 functions as the back gate of this memory access transistor, and receives a negative voltage Vbb. The potential of third level conductive layer 904 is determined depending upon the stored data. As depicted by the broken line in FIG. 69, the charge stored in the memory capacitor is reduced by the leakage current through the junction capacitance of storage node SN (the PN junction between impurity region 901b and substrate region 900), the leakage current through the channel region beneath second conductive layer and the leakage current to capacitor insulation film 905.
FIG. 70 represents a time dependent change in the potential level of storage node SN. The change shown in FIG. 70 is encountered in the case where precharge voltage VBL (=VCCS/2) is applied to bit line BL and ground voltage VSS is applied to word line WL (subword line SWL). Voltage V (SN) of storage node SN has the time dependency represented by the following equation due to leakage current.
V(SN)≈Vbb+(VCCSxe2x88x92Vbb)xc2x7exp (xe2x88x92T/xcfx84a),
where T represents the time and coefficient xcfx84a is the characteristic value indicating the charge retention characteristic when H level data is written to the memory cell. A larger characteristic value xcfx84a indicates a longer charge retention time of the memory cell.
When data of an H level is written into storage node NS, voltage V (SN) of the storage node corresponds to the level of sense power supply voltage VCCS. Storage node voltage V (SN) is gradually reduced according to the leakage current through the junction at the elapse of time T. In the case where memory cell data is read out to the bit line when the storage node voltage V(SN) is Vcr at time T1, the voltage difference between the bit lines, (Vcrxe2x88x92VBL)xc2x7(Cs/(Cs+Cb)), becomes lower than the sensitivity of the sense amplifier. Here, Cs and Cb represent the parasitic capacitances of the memory cell capacitor and bit line, respectively. More specifically, at the elapse of time T1, the sense amplifier will operate erroneously to amplify H level data as L level data, resulting in H data readout error. It is therefore required to carry out refresh as to the memory cell within time T1. Characteristic value xcfx84a differs for each memory cell (by variation of a fabrication process parameter). The refresh interval is determined based on the worst case. In other words, refresh interval tREFmax is determined depending upon the shortest data retaining time i.e. the smallest value of characteristic value xcfx84a in the semiconductor memory device.
As to the process of an embedded DRAM, a fabrication process identical to that of the logic integrated on the same chip is employed. In order for the transistors of the logic to exhibit the full performance, the process such as the salicide process to the source and drain diffusion layers of the transistor, which is the standard in the process of the logic, is also introduced in the process of the embedded DRAM. Therefore, the thermal budget of a high temperature thermal process, the product of the execution time to temperature of thermal process, for the formation of the memory capacitor is reduced. This means that a thermal process at a predetermined temperature for a sufficient period of time cannot be applied to the impurity region and insulation film for the embedded DRAM, compared to that of a general purpose of standard DRAM. Therefore, the junction leakage current and leakage current through the capacitor insulation film is slightly greater in the embedded DRAM.
When a cylindrical stacked capacitor cell structure as shown in FIG. 50 is employed, there will be a great step gradation between the DRAM area and the logic area. Although the interlayer insulation film between the interconnection lines can be planarized to a certain level by the CMP (chemical-mechanical polishing) process, this stepped gradation cannot be eliminated completely. The irregular reflection of the reflected light at the stepped portion in the exposure step of the photolithography process will impede the sufficient reduction of the pitch of the metal interconnection lines. It is therefore difficult to realize a metal interconnection line pitch that is required in the library of high density of the logic. With a penalty, to some extent, of the capacitance of the memory cell capacitor, the height of the storage node of the stacked capacitor (reduce the height of the cylindrical portion) is reduced to completely planarize the interlayer insulation film between the interconnection lines, aiming to eliminate the stepped gradation between the DRAM and the logic for increasing the gate density of the logic library. Thus, the capacitance of the memory cell capacitor is smaller than that of the general purpose DRAM. Accordingly, the amount of stored charge is also reduced.
The embedded DRAM is integrated, on a common semiconductor chip, together with the logic unit that operates at high speed. The temperature of the embedded DRAM is apt to become higher than that of the general purpose DRAM by heat transfer from the logic unit that operates at high speed. Furthermore, the power supply line and the substrate of the embedded DRAM is susceptible to noise due to the high speed operation of the logic unit. By these various factors of the process and chip operation, the refresh characteristics of the embedded DRAM is made inferior to that of the general purpose DRAM. Furthermore, the refresh interval of the embedded DRAM must be set shorter than that of the general purpose DRAM, inducing increase in the consumed current for retaining data.
When the operation of the logic unit is ceased as in a sleep mode, the self refresh operation of executing refresh periodically must be carried out to retain the data stored in the embedded DRAM. Since the refresh interval in the self refresh mode becomes shorter than that of the general purpose DRAM, the current consumption in the sleep mode is also increased. Particularly in the case where a system LSI employing an embedded DRAM is applied to the products, such as portable information equipment and digital cameras, driven by battery, reduction in power consumption will become a more important factor than the increase of the storage capacity. Thus, increase of current consumption in accordance with degradation of the refresh characteristics will become a more significant problem in the application to equipment driven by battery.
Moreover, since the DRAM is integrated on a semiconductor substrate common to that of the logic, it is preferable for the embedded DRAM to operate following the operation speed of the logic, to reduce the waiting time of the logic. To this end, the conventional embedded DRAM employs the hierarchical word line structure to reduce the time required for row selection. Therefore, it is preferable not only to reduce current consumption and but also to minimize the row access time (the time required for row selection).
An object of the present invention is to provide semiconductor memory device that can have current consumption reduced.
Another object of the present invention is to provide an embedded DRAM improved in refresh characteristics.
A further object of the present invention is to provide a semiconductor memory device that can have power consumption and row access time reduced.
Still another object of the present invention is to provide an embedded DRAM improved in both refresh characteristics and row access time.
A still further object of the present invention is to provide a semiconductor memory device of low current consumption, in which a defect in rows can be repaired efficiently.
Yet a further object of the present invention is to provide a semiconductor memory device that operates in a twin cell mode with improved repair efficiency of a defective row.
According to an aspect of the present invention, a semiconductor memory device includes a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged corresponding to the rows, each word line having memory cells of a corresponding row connected thereto, and a plurality of bit lines arranged corresponding to the columns, each bit line having memory cells of a corresponding column connected thereto. The plurality of bit lines are arranged in pairs. Each memory cell is arranged corresponding to a crossing of one bit line in a pair and a corresponding word line.
The semiconductor memory device according to one aspect of the present invention includes row select circuitry for simultaneously selecting word lines of an addressed row and a related row according to an address signal. The row select circuitry selects the related row according to an address such that a memory cell is arranged corresponding to each crossing between the addressed row and related row and the bit lines in a pair. The row select circuitry includes a drive circuit for driving the addressed row and related row to selected states individually.
The semiconductor memory device according to one aspect of the present invention further includes a sense amplifier circuit arranged corresponding to each bit line pair to amplify differentially the potential of the corresponding bit line pair when made active.
According to another aspect of the present invention, a semiconductor memory device includes a plurality of memory subarrays each having a plurality of memory cells arranged in rows and columns, a plurality of subword lines arranged corresponding to the memory cell rows in each memory subarray, each subword line having memory cells of a corresponding row connected thereto, a plurality of main word lines arranged extending in the row direction commonly to the plurality of memory subarrays, each main word line arranged corresponding to a predetermined number of subword lines in each memory subarray, and a plurality of subword line drivers arranged corresponding to the plurality of subword lines, each subword line driver driving a corresponding subword line to a selected state according to a signal on a corresponding main word line and subdecode signal. The subdecode signal identifies simultaneously two subword lines out of the predetermined number of subword lines.
The semiconductor memory device according to the another aspect of the present invention further includes a plurality of bit line pairs provided corresponding to memory cell columns in each memory subarray, each bit line pair having memory cells of a corresponding column connected thereto, and a plurality of sense amplifier circuits provided corresponding to the plurality of bit line pairs, each sense amplifier circuit amplifying differentially the voltages of a corresponding bit line pair. A memory cell is connected to the bit lines in each bit line pair, correspondingly to each crossing of the bit lines and the two subword lines identified simultaneously by the subdecode signal. The subword line pair identified simultaneously by the subdecode signal is connected at their both ends by conductive layers.
According to a further aspect of the present invention, a semiconductor memory device includes a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged corresponding to the rows of memory cells, each word line having memory cells of a corresponding row connected thereto, a plurality of column lines arranged corresponding to the columns of memory cells, each column line having memory cells of a corresponding column connected thereto, and a plurality of column voltage hold circuits provided corresponding to the plurality of column lines to hold corresponding column lines at a predetermined voltage level in a standby state. The plurality of column voltage hold circuits transmit the current-limited voltage to the corresponding column lines as the predetermined voltage.
According to a still further aspect of the present invention, a semiconductor memory device includes: a plurality of normal memory cells arranged in rows and columns; a plurality of normal subword lines arranged corresponding to each normal memory cell row, each normal subword line having normal memory cells of a corresponding row connected thereto; a plurality of normal main word lines each arranged corresponding to a predetermined number of normal subword lines; a plurality of spare memory cells arranged in at least the predetermined number of rows; a plurality of spare subword lines arranged corresponding to these rows of spare memory cells, each spare subword line having spare memory cells of a corresponding row connected thereto; at least one spare main word line arranged corresponding to the predetermined number of subword lines out of the plurality of spare subword lines; a first spare determination circuit determining whether a defective normal subword line is specified or not according to an address signal; a second spare determination circuit determining whether a defective normal main word line is specified or not according to the address signal; a normal row select circuit selectively driving a normal main word line and a normal subword line to a selected state according to the address signal and the output signals of the first and second determination circuits; and a spare row select circuit selectively driving a spare main word line and a spare subword line to a selected state according to the address signal and the output signals of the first and second determination circuits.
The normal row select circuit brings a normal main word line and a corresponding normal subword line to a non-selected state when the first determination circuit detects a defect, and drives an addressed main word line to a selected state and an addressed normal subword line to a selected state while maintaining a predetermined normal subword line out of the predetermined number of corresponding normal subword lines at a non-selected state independent of the address signal when the second determination circuit detects a defect.
The spare row select circuit drives a corresponding spare main word line and spare subword line to a selected state according to an address signal when the first determination circuit detects a defect, and selectively drives a corresponding spare main word line to a selected state and a spare subword line corresponding to the address signal to a selected state while maintaining a spare subword line excluding the spare subword line corresponding to the predetermined normal subword line among corresponding spare subword lines at a non-selected state when the second determination circuit detects a defect.
According to yet a further aspect of the present invention, a semiconductor memory device includes a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged corresponding to the memory cell rows and each having memory cells of a corresponding row connected thereto, and a row select circuit to drive to a selected state simultaneously a pair of word lines with one word line interposed therebetween out of the plurality of word lines.
Preferably, a bit line pair is arranged corresponding to each memory cell column. The memory cells are arranged so that, in a particular operation mode, complementary data is read out to each bit line pair, and when one word line is selected in a normal operation mode, memory cell data is read out to one bit line in each bit line pair.
Information of one bit is stored by two memory cells. Complementary data is written into these two memory cells by the sense amplifier circuit. In selection of a memory cell, a pair of bit lines has complementary signals transmitted thereon, and accordingly the potential difference between the bit lines is increased. Therefore, even if the charge in the memory cell storing H level data is reduced by leakage current, sufficient potential difference can be generated between the bit lines. Accordingly, the refresh interval can be lengthened. Thus, the number of times of refresh operations in the data holding mode can be reduced to reduce power consumption.
Since the subword lines driven simultaneously to a selected state are connected by the conductive layers at respective both ends thereof so as to be driven by the subword line driver from both sides, the subword lines can be driven to the selected state at high speed. Accordingly, memory cell data can be read out to the bit line pair at high speed. This means that the sense start timing of sense amplifier circuit can be set faster to reduce the row access time.
By transmitting a predetermined voltage (precharge voltage) through a current limiting facility to the bit lines, leakage current in a standby mode through micro short between a bit line and a subword line, if any, can be reduced. Accordingly, current consumption can be reduced even in the case where many micro shorts are present.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.